how VHDL – PhysDesignRules:367
I am getting a warning when i try synthesize,implement, and generate program file from my VHDL Code.
When i try to synthesize i get this error
When i Implement it i get this
and when i generate program file i get this error
What could cause this error..
: http://pastebin.com/eK05tyEb – link to the code
User constrain file /.Ucf
Your code as you have posted may not tell the entire story. Normally there is an interface (user constraints, thanks Bob) file that defines pin edge inputs and outputs to a port of a circuit internal to the FPGA you define. I am not seeing that.
Secondly, I also see in your code that you have 2 differing circuits driving each one of your output LEDs.
You have an if statement that checks for BTN_3 being 1, which will drive ALL of the LEDs to 0, then a set of If statements checking the input state of each “Switch_X” which individually drives a 0 or one to each LED. This is actually illegal. You can only have one circuit driving any output port.
What you should do is write this circuit as follows:
What I have essentially done is to bring all of your individual Switch_X checking into the else clause of the btn_3 check. This forces what I was stating before, that only one logic circuit will drive any LED at any point in time.