how VHDL – PhysDesignRules:367

 

Questions


I am getting a warning when i try synthesize,implement, and generate program file from my VHDL Code.

When i try to synthesize i get this error

WARNING:Xst:647 - Input <BTN_3> is never used. 
    This port will be preserved and left unconnected if it 
    belongs to a top-level block or it belongs to a sub-block and 
    the hierarchy of this sub-block is preserved.

When i Implement it i get this

WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. The signal
    does not drive any load pins in the design.
WARNING:Par:288 - The signal BTN_3_IBUF has no load.  
    PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. 
    This design will cause Bitgen to issue DRC warnings.

and when i generate program file i get this error

WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. 
    The signal does not drive any load pins in the design.

What could cause this error..
The code can be found here [http://pastebin.com/eK05tyEb][1]

[1]: http://pastebin.com/eK05tyEb – link to the code

User constrain file /.Ucf

NET "Switch_0" LOC = "G18";
    NET "Switch_1" LOC = "H18";
    NET "Switch_2" LOC = "K18";
    NET "Switch_3" LOC = "K17";
    NET "Switch_4" LOC = "L14";
    NET "Switch_5" LOC = "L13";
    NET "Switch_6" LOC = "N17";
    NET "Switch_7" LOC = "R17";
    NET "LED_0" LOC = "J14";
    NET "LED_1" LOC = "J15";
    NET "LED_2" LOC = "K15";
    NET "LED_3" LOC = "K14";
    NET "LED_4" LOC = "E17";
    NET "LED_5" LOC = "P15";
    NET "LED_6" LOC = "F4";
    NET "LED_7" LOC = "R4";
    NET "BTN_3" LOC = "H13";

 

 

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Answer

Your code as you have posted may not tell the entire story. Normally there is an interface (user constraints, thanks Bob) file that defines pin edge inputs and outputs to a port of a circuit internal to the FPGA you define. I am not seeing that.

Secondly, I also see in your code that you have 2 differing circuits driving each one of your output LEDs.

You have an if statement that checks for BTN_3 being 1, which will drive ALL of the LEDs to 0, then a set of If statements checking the input state of each “Switch_X” which individually drives a 0 or one to each LED. This is actually illegal. You can only have one circuit driving any output port.

What you should do is write this circuit as follows:

architecture Behavioral of Switch_led is
begin
  Process(Switch_0, Switch_1, Switch_2, Switch_3, Switch_4, Switch_5, Switch_6 , Switch_7, BTN_3)
  begin

    if BTN_3 = '1' then 
      Led_0 <= '0';
      Led_1 <= '0';
      Led_2 <= '0';
      Led_3 <= '0';
      Led_4 <= '0';
      Led_5 <= '0';
      Led_6 <= '0';
      Led_7 <= '0';
    else

      if Switch_0 = '1' then
        Led_0 <= '1';
      else
        Led_0 <= '0';
      end if;

      if Switch_1 = '1' then
        Led_1 <= '1';
      else
        Led_1 <= '0';
      end if;

      if Switch_2 = '1' then
        Led_2 <= '1';
      else
        Led_2 <= '0';
      end if;

      if Switch_3 = '1' then
        Led_3 <= '1';
      else
        Led_3 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_5 = '1' then
        Led_5 <= '1';
      else
        Led_5 <= '0';
      end if;

      if Switch_6 = '1' then
        Led_6 <= '1';
      else
        Led_6 <= '0';
      end if;

      if Switch_7 = '1' then
        Led_7 <= '1';
      else
        Led_7 <= '0';
      end if;

    end if;

  end process;
end Behavioral;

What I have essentially done is to bring all of your individual Switch_X checking into the else clause of the btn_3 check. This forces what I was stating before, that only one logic circuit will drive any LED at any point in time.

fpga,if-statement,vhdl

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